
#define CACHE_WRITETHROUGH		0x01	// Caches are writethrough
#define CACHE_READTHROUGH		0x02	// Caches are readthrough
#define CACHE_PREDICT_MISS		0x04	// Start reading the next cache
										// immediately
struct mmu_cache {
	cache_policy	policy;
	cache_stats		stats;
	sim_cycle		hit_cost;
	CACHE			*cache;
	mmu_q			q;
};


